Because the subsystem is hierarchical, it enables the use of timing constraints from the infrastructure cores. The subsystem automatically picks up the constraints from the sub cores. The timing constraints related to MII, GMII, RGMII interfaces are provided by Tri-Mode Ethernet MAC core. The timing constraints related to VLAN and others are provided by the AXI Ethernet Buffer. The timing constraints related to the transceiver and elastic buffers are provided by the 1G/2.5G Ethernet PCS/PMA or SGMII core.
In addition to the sub-cores constraints, the placement constraints should be provided at the top.
When a project is targeted for a board, you can use Board Based IO Constraints generation. On selection of the board interface, the constraints for that interface are generated automatically. The subsystem propagates the required inputs to the sub cores and these generate the constraints in their file list. These constraints are usually available in a file that has file name ending with _board.xdc.