Reset and Address Filter Register - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)
Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

The Reset and Address Filter (RAF) register is shown in the following figure. This registerallows the software to block reception of multicast and broadcast Ethernet frames. The multicast reject bit provides a means of blocking receive multicast Ethernet frames without having to clear out any multicast address values stored in the multicast address table. It also provides a means for allowing more than four multicast addresses to be received (the limit of the multicast address table). To accept more than four multicast addresses, the FMI register is set to promiscuous mode and the multicast reject bit of this register set to allow multicast frames. See for more information.

The software might also need to filter out additional receive frames with other addresses. The broadcast reject bit provides the only means for rejecting receive broadcast Ethernet frames.

As additional functionality was added to the subsystem, bits in this register are used to control those new functions. To minimize the effect of these new bits on existing applications the default values of these bits disable this functionality. This ensures that when applications do not use the more recent functionality, the subsystem operates the way it did previously.

Figure 1. Reset and Address Filter Register (0x0000_0000) AXI Ethernet Page-1 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.102 12 12 Sheet.103 31 31 Sheet.104 15 15 Sheet.105 13 13 Sheet.106 10 10 Sheet.107 11 11 Sheet.108 Reserved Reserved Sheet.109 BcstRej BcstRej Sheet.110 RxBadFrmEn RxBadFrmEn Sheet.111 McstRej McstRej Sheet.112 X14025 X14025 Sheet.113 MSB MSB Sheet.114 LSB LSB Sheet.115 9 9 Sheet.116 8 8 Sheet.117 7 7 Sheet.118 6 6 Sheet.119 5 5 Sheet.120 4 4 Sheet.121 3 3 Sheet.122 14 14 Sheet.123 2 2 Sheet.124 1 1 Sheet.125 0 0 Sheet.126 TxVTagMode TxVTagMode Sheet.127 RxVTagMode RxVTagMode Sheet.128 TxVStrpMode TxVStrpMode Sheet.129 RxVStrpMode RxVStrpMode Sheet.130 NewFncEnbl NewFncEnbl Sheet.131 EMultiFltrEnbl EMultiFltrEnbl Sheet.132 Reserved Reserved Sheet.133 Reserved Reserved Standard Arrow Standard Arrow.2 Standard Arrow.59 Standard Arrow.60 Standard Arrow.61 Standard Arrow.62 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22

The following table shows the Reset and Address Filter register bit definitions.

Table 1. Reset and Address Filter Register (0x000_000)
Bits Name Access Reset Value Description
31:15 Reserved RO 0x0 Reserved: These bits are reserved for future use and always return zero.
14 RxBadFrmEn R/W 0 Receive Bad Frame Enable: This bit provides a means for allowing bad receive frames to be accepted and passed to the RX AXI4-Stream interface as if they were good frames.
  • 0 – Normal operation, bad frames are rejected.
  • 1 – Bad frames are accepted.
13 Reserved RO 0 Reserved: These bits are reserved for future use and always return zero.
12 EMultiFltrEnbl R/W 0 Enhanced Multicast Filter Enable: This bit provides a simple way to disable the new enhanced multicast filtering if present. This is necessary if promiscuous address reception mode is desired or if use of the built-in 4 TEMAC multicast address registers is required when the subsystem includes the enhanced multicast address filtering function enabled at build time by the C_MCAST_EXTEND parameters. See for more details.
  • 0 – Disable enhanced multicast address filtering mode.
  • 1 – Enable enhanced multicast address filtering mode if present.
11 NewFncEnbl R/W 0 New Functions Enable: This bit allows you to disable VLAN tagging, VLAN stripping, VLAN translation, and extended multicast filtering. Enabling the new functions only affect operation if the functions have been added to the design using the appropriate parameters at build-time.
  • 0 – Disable new functions.
  • 1 – Enable new functions if present.
10:9 RxVStrpMode R/W 00 Receive VLAN Strip Mode: These bits select the operation mode for receive VLAN stripping and are only used when C_RXVLAN_STRP = 1. Valid VLAN TPID values must be initialized in the TPID0 and TPID1 registers. For mode 11, the Receive VLAN data table must be initialized. See for more details.
  • 00 – No VLAN tags are stripped from receive frames.
  • 01 – One VLAN tag are stripped from all receive frames that have VLAN tags.
  • 10 – Reserved.
  • 11 – One VLAN tag is stripped from select receive frames that already have VLAN tags.
8:7 TxVStrpMode R/W 00 Transmit VLAN Strip Mode: These bits select the operation mode for transmit VLAN stripping and are only used when C_TXVLAN_STRP = 1. Valid VLAN TPID values must be initialized in the TPID0 and TPID1 registers. For mode 11, the Transmit VLAN data table must be initialized. See for more details.
  • 00 – No VLAN tags are stripped from transmit frames.
  • 01 – One VLAN tag is stripped from all transmit frames that have VLAN tags.
  • 10 – Reserved.
  • 11 – One VLAN tag is stripped from select transmit frames that already have VLAN tags.
6:5 RxVTagMode R/W 00 Receive VLAN Tag Mode: These bits select the operation mode for receive VLAN tagging and are only used when C_RXVLAN_TAG = 1. The VLAN tag that is added is from the RTAG register. Valid VLAN TPID values must be initialized in the TPID0 and TPID1 registers. For mode 11, the Receive VLAN data table must be initialized. See for more details.
  • 00 – No VLAN tags are added to receive frames.
  • 01 – VLAN tags are added to all receive frames.
  • 10 – VLAN tags are added to all receive frames that already have a VLAN tag.
  • 11 – VLAN tags are added to select receive frames that already have VLAN tags.
4:3 TxVTagMode R/W 00 Transmit VLAN Tag Mode: These bits select the operation mode for transmit VLAN tagging and are only used when C_TXVLAN_TAG = 1. The VLAN tag that is added is from the TTAG register. Valid VLAN TPID values must be initialized in the TPID0 and TPID1 registers. For mode 11, the Transmit VLAN data table must be initialized. See for more details.
  • 00 – No VLAN tags are added to transmit frames.
  • 01 – VLAN tags are added to all transmit frames.
  • 10 – VLAN tags are added to all transmit frames that already have a VLAN tag.
  • 11 – VLAN tags are added to select transmit frames that already have VLAN tags.
2 BcstRej R/W 0 Reject Receive Broadcast Destination Address: This bit provides a means for accepting or rejecting broadcast Ethernet frames.
  • 0 – Accept receive broadcast destination address Ethernet frames.
  • 1 – Reject all receive broadcast destination address Ethernet frames. This is the only method available for blocking broadcast Ethernet frames.
1 McstRej R/W 0 Reject Receive Multicast Destination Address: This bit provides a means for accepting or rejecting multicast Ethernet frames.
  • 0 – Accept receive multicast destination address Ethernet frames that meet address filtering specified in FMI register and/or the multicast address table.
  • 1 – Reject all receive multicast destination address Ethernet frames regardless of FMI register and multicast address table.
0 Reserved RO 0 Reserved: These bits are reserved for future definition and always return zero.