The SGMII can also be implemented over LVDS. For more details on this mode, refer to the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047). When the core is configured in the Include Shared Logic in Core mode, the input differential reference clock frequency can be selected from 125 MHz, 156.25 MHz and 625 MHz for AMD UltraScale™ devices.
In UltraScale devices, for the SGMII interface, an option is provided to choose between Synchronous SGMII over LVDS and Asynchronous SGMII over LVDS using the parameter, EnableAsyncSGMII.
The synchronous SGMII over LVDS solution uses component mode I/Os such as ISERDES, OSERDES, IDELAY, ODELAY components whereas the asynchronous implementation uses native mode HSSIO components such as BITSLICE and BITSLICE_CONTROL.
When using SGMII over LVDS in AMD UltraScale+™
or AMD Versal™
devices or using the
Asynchronous SGMII over LVDS solution in AMD UltraScale™
devices, refer to
the
1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product
Guide (PG047) for port descriptions (especially for RIU
interface, dly_rdy , vtc_rdy ports) and constraints
relating to the design in the "Asynchronous 1000BASE-X/SGMII over LVDS" section in the
1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product
Guide (PG047). For Versal devices,
Asynchronous SGMII over LVDS is implemented using Advanced I/O Wizard.