Simulation - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID

PG138

Release Date

2023-11-15

Version

7.2 English

For comprehensive information about Vivado simulation components, as well as information about using supported third-party tools, see the Vivado Design Suite User Guide: Logic Simulation (UG900).

Important: For cores targeting 7 series or AMD Zynq™ 7000 devices, UNIFAST libraries are not supported. AMD IP is tested and qualified with UNISIM libraries only.

Includes all simulation sources required by the core. Simulation of the core is not supported without the addition of a test bench (not supplied). Simulation of the example design is supported.

When SIMULATION_MODE is set, the link timer for auto-negotiation is pre-loaded with a smaller value. When SIMULATION_MODE is set, the core also pre-loads the 3 ms counter for the 7 series transceiver in startup FSM with a smaller value to decrease the simulation time.

For SGMII over LVDS, setting SIMULATION_MODE pre-loads the eye_mon_wait_time counter to a lower value to decrease the simulation time.

Note: The SIMULATION_MODE generic is provided in all modes to reduce simulation time. In simulation, the value of SIMULATION_MODE should be 1. In implementation, the value of SIMULATION_MODE should be 0. To change the SIMULATION_MODE attribute you need to use the following command before the generation of the output products:

set_property CONFIG.SIMULATION_MODE {1} [get_ips <component_name> ]

Important: SIMULATION_MODE generic should be set to 1 only for simulation.

Note: In case of Asynchronous SGMII/1000BASE-X over LVDS solution, SIMULATION_MODE should be 1 to simulate the design in post-synthesis and post-implementation simulations. This is because the RIU register used in the calibration sequence in the clock_reset module is not supported in simulation and always returns 0 value when read. However, SIMULATION_MODE should be set to 0 when the design is implemented in FPGA. It should be reset to 0.

When SGMII or 1000Base-X is selected as the PHY type, a mixed hardware description language (HDL) license is required to successfully run the simulation.