TEMAC Transmit Configuration Register - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)
Document ID
PG138
Release Date
2023-11-15
Version
7.2 English
Table 1. TEMAC Receive Configuration Word1 (RCW1) Register (0x404)
Bits Name Access Reset Value Description
31 RST R/W 0 Reset: When this bit is 1, the receiver is reset. The bit automatically resets to 0. The reset also sets all of the receiver configuration registers to their default values. Resetting the receiver without resetting the subsystem can place the subsystem in an unknown state.
  • 0 – no reset
  • 1 – initiate a receiver reset
30 JUM 1 R/W 0 Jumbo Frame Enable: When this bit is 1 the receiver accepts frames over the maximum length specified in IEEE Std 802.3-2002 specification.
  • 0 – receive jumbo frames disabled
  • 1 – receive jumbo frames enabled
29 FCS R/W 0 In-Band FCS Enable: When this bit is 1, the receiver provides the FCS field with the rest of the frame data. When this bit is 0 the FCS field is stripped from the receive frame data. In either case the FCS field is verified.
  • 0 – strip the FCS field from the receive frame data
  • 1 – provide the FCS field with the receive frame data
28 RX 2 R/W 1 Receive Enable: When this bit is 1, the receiver logic is enabled to operate. When this bit is 0, the receiver ignores activity on the receive interface.
  • 0 – receive disabled
  • 1 – receive enabled
27 VLAN R/W 0 VLAN Frame Enable: When this bit is 1, the receiver accepts VLAN tagged frames. The maximum payload length increases by four bytes.
  • 0 – receive of VLAN frames disabled
  • 1 – receive of VLAN frames enabled
26 HD R/W 0 Half-Duplex Mode: When this bit is 1, the receive operates in half-duplex mode. When this bit is 0, the receiver operates in full-duplex mode. Only full-duplex is supported so this bit should always be set to 0.
  • 0 – full-duplex receive
  • 1 – half-duplex receive
25 LT_DIS R/W 0 Length/Type Field Valid Check Disable: When this bit is 1, it disables the Length/Type field check on the receive frame.
  • 0 – perform Length/Type field check
  • 1 – do not perform Length/Type field check
24 CL_DIS R/W 0x0 Control Frame Length Check Disable: When this bit is 1, control frames larger than the minimum frame length can be accepted
23 Reserved     Reserved .
22   R/W 0

Inband 1588 Timestamp Enable.

When 0, Timestamp is only provided out-of-band. When 1, the Timestamp is provided in-Line in addition to out-of-band.

When the TEMAC does not include 1588 functionality, this bit is ignored because no timestamp is present.
21:16 Reserved RO 0x0 Reserved: These bits are reserved for future use and always return zero.
15:0 PauseAddr R/W 0xFFFF Pause Frame Ethernet MAC Address (47:32): This address is used to match the destination address of any received flow control frames. It is also used as the source address for any transmitted flow control frames.

This address is ordered so that the first byte transmitted/ received is the lowest position byte in the register. For example, an Ethernet MAC address of AA-BB-CC-DD-EE-FF would be stored in the PauseAddr(47:0) as 0xFFEEDDCCBBAA.
  1. Extended VLAN function require that jumbo frames be enabled.
  2. This bit enables basic VLAN operation that is native to the TEMAC core. The TEMAC core recognizes VLAN frames when the Type/Length field contains a VLAN TAG with a TPID value of 0x8100. No other TPID values are recognized. Extended VLAN mode described later allow programmable TPID values. This bit must be 0 (disabled) when using extended VLAN mode.

The TEMAC Transmit Configuration (TC) register is shown in the following figure. This register can be written at any time but the transmitter logic only applies the configuration changes during Inter-Frame gaps. The exception to this is the Reset bit, which is effective immediately.

Figure 1. TEMAC Transmit Configuration Register (0x408) AXI Ethernet Page-1 Sheet.1 Sheet.2 Sheet.4 Sheet.5 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.13 Reserved Reserved Sheet.14 RST RST Sheet.15 FCS FCS Sheet.16 VLAN VLAN Sheet.17 IFG IFG Sheet.18 TX TX Sheet.19 JUM JUM Sheet.20 HD HD Sheet.23 MSB MSB Sheet.24 LSB LSB Sheet.25 25 25 Sheet.27 24 24 Sheet.30 26 26 Sheet.31 27 27 Sheet.32 28 28 Sheet.33 29 29 Sheet.34 30 30 Sheet.35 31 31 Sheet.36 0 0 Standard Arrow.1 Sheet.38 X14041 X14041 Standard Arrow.5 Standard Arrow.6 Standard Arrow.7 Arrow - Standard.8 Standard Arrow.19 Standard Arrow.20 Standard Arrow.21

The following table shows the TEMAC Transmit Configuration register bit definitions.

Table 2. TEMAC Transmit Configuration Register (0x408)
Bits Name Access Reset Value Description
31 RST R/W 0 Reset: When this bit is 1, the transmitter is reset. The bit automatically resets to 0. The reset also sets all of the transmitter configuration registers to their default values. Resetting the transmitter without resetting the subsystem can place the subsystem in an unknown state.
  • 0 – no reset
  • 1 – initiate a transmitter reset
30 JUM 1 R/W 0 Jumbo Frame Enable: When this bit is 1 the transmitter sends frames over the maximum length specified in IEEE Std 802.3-2002 specification.
  • 0 – send jumbo frames disabled
  • 1 – send jumbo frames enabled
29 FCS R/W 0 In-Band FCS Enable: When this bit is 1, the transmitter accepts the FCS field with the rest of the frame data. When this bit is 0 the FCS field is calculated and supplied by the transmitter. In either case the FCS field is verified.
  • 0 – transmitter calculates and sends FCS field
  • 1 – FCS field is provided with transmit frame data
28 TX 2 R/W 1 Transmit Enable: When this bit is 1, the transmit logic is enabled to operate.
  • 0 – transmit disabled
  • 1 – transmit enabled
27 VLAN R/W 0 VLAN Frame Enable: When this bit is 1, the transmitter allows transmission of VLAN tagged frames.
  • 0 – transmit of VLAN frames disabled
  • 1 – transmit of VLAN frames enabled
26 HD R/W 0 Half-Duplex Mode: When this bit is 1, the transmitter operates in half-duplex mode. When this bit is 0, the transmitter operates in full-duplex mode. Only full-duplex is supported so this bit should always be set to 0 .
  • 0 – full-duplex transmit
  • 1 – half-duplex transmit
25 IFG R/W 0 Inter Frame Gap Adjustment Enable: When this bit is 1, the transmitter uses the value of the IFGP register (Transmit Inter Frame Gap Adjustment Register) to extend the transmit Inter Frame Gap beyond the minimum of 12 idle cycles (96-bit times on the Ethernet Interface).
  • 0 – no IFGP adjustment enabled
  • 1 – IFGP adjusted based on IFGP register
24:23   RO   Reserved
22   RW  

Inband 1588 Command Field Enable.

When 0, the Command Field is provided out-of-band. When 1, the Command Field is provided in-Line.

When the TEMAC does not include 1588 functionality, this bit is ignored because no Command Field is present.
21:0   RO   Reserved: These bits are reserved for future use and always return zero.
  1. Extended VLAN function require that jumbo frames be enabled.
  2. This bit enables basic VLAN operation that is native to the TEMAC core. The TEMAC core recognizes VLAN frames when the Type/Length field contains a VLAN TAG with a TPID value of 0x8100. No other TPID values are recognized. Extended VLAN mode described later allow programmable TPID values. This bit must be 0 (disabled) when using extended VLAN mode.