The Transmit Inter Frame Gap Adjustment (IFGP) register is shown in the following figure. This register provides a duration value of Inter Frame Gap when enabled by the TC register (). When enabled, the TEMAC uses the value of this register to extend the Inter Frame Gap beyond the minimum of 12 idle cycles which is 96-bit times on the Ethernet Interface.
Figure 1. Transmit Inter Frame Gap Adjustment Register (0x0000_0008)
The following table shows the Transmit Inter Frame Gap Adjustment register bit definitions.
Bits | Name | Access | Reset Value | Description |
---|---|---|---|---|
31:8 | Reserved | RO | 0x0 | Reserved: These bits are reserved for future use and always return zero. |
7:0 | IFGP0 | R/W | 0x0 | Transmit Inter Frame Gap Adjustment Value: This 8-bit value can be used along with the Inter Frame Gap Adjustment Enable bit of the Transmit Configuration register (25) to increase the Transmit Inter Frame Gap. This value is the width of the IFG in idle cycles. Each idle cycle is 8 bit times on the Ethernet interface. The minimum IFG time is 12 idle cycles which is 96 bit-times. If this field value is less than 12 or if IFGP adjustment is disabled in the Transmit Configuration register, an IFGP of 12 idle cycles (96-bit times) is used. |