Transmit Inter Frame Gap Adjustment Register - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

The Transmit Inter Frame Gap Adjustment (IFGP) register is shown in the following figure. This register provides a duration value of Inter Frame Gap when enabled by the TC register (). When enabled, the TEMAC uses the value of this register to extend the Inter Frame Gap beyond the minimum of 12 idle cycles which is 96-bit times on the Ethernet Interface.

Figure 1. Transmit Inter Frame Gap Adjustment Register (0x0000_0008) AXI Ethernet Page-1 Layer_1 Sheet.3 Sheet.4 Sheet.10 Sheet.12 31 31 Sheet.13 Reserved Reserved Sheet.14 IFGP IFGP Sheet.15 X14027 X14027 Sheet.16 MSB MSB Sheet.17 LSB LSB Sheet.18 8 8 Sheet.19 7 7 Sheet.20 0 0 Sheet.21 Sheet.1

The following table shows the Transmit Inter Frame Gap Adjustment register bit definitions.

Table 1. Transmit Inter Frame Gap Adjustment Register (0x0000_0008)
Bits Name Access Reset Value Description
31:8 Reserved RO 0x0 Reserved: These bits are reserved for future use and always return zero.
7:0 IFGP0 R/W 0x0 Transmit Inter Frame Gap Adjustment Value: This 8-bit value can be used along with the Inter Frame Gap Adjustment Enable bit of the Transmit Configuration register (25) to increase the Transmit Inter Frame Gap. This value is the width of the IFG in idle cycles. Each idle cycle is 8 bit times on the Ethernet interface. The minimum IFG time is 12 idle cycles which is 96 bit-times. If this field value is less than 12 or if IFGP adjustment is disabled in the Transmit Configuration register, an IFGP of 12 idle cycles (96-bit times) is used.