Transmit Statistics Vector - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)
Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

The transmitter provides 32 bits of statistics for each frame transmitted and a signal which can be used to count the total number of bytes transmitted. Statistics information is provided using a 32-bit vector for one clock cycle, as shown in the following table. The following table shows the bit definition of the transmit statistics. Bits 28 to 20 are always driven to zero because half-duplex is not supported.

The waveform in the following table represents the statistics counter updates for the corresponding vector bits. The entire vector otherwise is not accessible through an addressable register or available on the external ports.

Figure 1. TEMAC Transmit Statistics Waveforms AXI Ethernet Page-1 Text Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 Sheet.8 Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 Sheet.22 Sheet.23 Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Sheet.33 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Sheet.38 Sheet.39 Sheet.40 Sheet.41 Sheet.42 Sheet.43 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Sheet.48 Sheet.49 Sheet.50 Sheet.51 Sheet.52 Sheet.53 TX data interface to PHY TX data interface to PHY Sheet.54 TxClientClk TxClientClk Sheet.55 ClientTxStatsByte Vld ClientTxStatsByte Vld Sheet.56 TX valid signal to PHY TX valid signal to PHY Sheet.57 ClientTxStats ClientTxStats Sheet.58 ( ( Sheet.59 31 31 Sheet.60 : : Sheet.61 0 0 Sheet.62 ) ) Sheet.63 ClientTxStatsVld ClientTxStatsVld Sheet.64 Sheet.65 Sheet.66 Sheet.67 Sheet.68 Ethernet Frame to PHY Ethernet Frame to PHY Sheet.69 X14085 X14085
Table 1. Transmit Statistics Bit Definitions
Bits Name Description
31 PAUSE_FRAME_TRANSMITTED Asserted if the previous frame was a pause frame initiated by writing to the Transmit Pause Frame (TPF) register.
30 BYTE_VALID TEMAC: Asserted if an Ethernet MAC frame byte (Destination Address to FCS inclusive) is in the process of being transmitted. This is valid on every clock cycle. Do not use this as an enable signal to indicate that data is present on the transmit data pins going to the PHY.
29 Reserved (driven to zero) Returns 0.
28:25 1 TX_ATTEMPTS(3:0) Full-Duplex: Returns 0s.
24 1 Reserved (driven to zero) Returns 0.
23 1 EXCESSIVE COLLISION Full-Duplex: Returns 0s.
22 1 LATE_COLLISION Full-Duplex: Returns 0s.
21 1 EXCESSIVE_DEFERRAL Full-Duplex: Returns 0s.
20 1 TX_DEFERRED Full-Duplex: Returns 0s.
19 VLAN_FRAME Asserted if the previous frame contains a VLAN identifier in the Length/Type field when transmitter VLAN operation is enabled.
18:5 FRAME_LENGTH_COUNT The length of the previous frame in number of bytes. The count sticks at 16,838 for jumbo frames larger than this value.
4 CONTROL_FRAME Asserted if the previous frame has the special Control type code 0x8808 in the Length/Type field.
3 UNDERRUN_FRAME Asserted if the previous frame contains an underrun error.
2 MULTICAST_FRAME Asserted if the previous frame contains a multicast address in the destination address field.
1 BROADCAST_FRAME Asserted if the previous frame contains a broadcast address in the destination address field.
0 SUCCESSFUL_FRAME Asserted if the previous frame is transmitted without error.
  1. Bits 28:20 are for Half-Duplex only. These bits return zero in Full-Duplex mode.