Transmit Timestamp Adjust Control Register - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)
Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

This register is present only when the TEMAC includes 1588 functionality. See the following table.

Table 1. Transmitter Timestamp Adjust Control Register (0x41C)
Bits Default Value Access Description
31:17 N/A RO Reserved
16 0 RW

Transmitter timestamp correction enable.

When 0, the transmitter timestamp is not adjusted. When 1, the transmitter timestamp is adjusted by the “TX latency adjust value”
15:0 0xD3 (211 ns) RW

TX latency adjust value.

In ToD mode: This value is in units of nanoseconds and is initialized to reflect the delay following the timestamping position through the MAC, 1000BASE-X FPGA logic, and GTX transceiver components.

In Correction Field Format: The default value is 387 ns decimal value.