Transmitter - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

The following figure shows the Transmitter portions of the Ethernet MAC and 1000BASE-X PHY enhanced with 1588 support.

Figure 1. Transmitter Block Level Diagram AXI Ethernet Page-1 Box.94 Box.2 2-D single, open.16 Sheet.4 Sheet.5 Sheet.6 Box.7 GT TX GTTX Box PHY TX PHY TX Sheet.9 PHY TX PHY TX Sheet.10 Sheet.11 Fixed Latency Fixed Latency Sheet.12 Sheet.13 Sheet.14 Fixed Latency Fixed Latency Box.73 Sheet.16 TX MAC extended with 1588 timestamping TX MAC extended with 1588 timestamping Box.84 Sheet.18 System Timer {seconds, nanoseconds} System Timer{seconds, nanoseconds} 2-D single, open.88 Sheet.20 Sheet.21 Sheet.22 Box.93 Adjust checksum Adjust checksum Sheet.24 Box.86 Timer Synchronise onto TX Ethernet clock Timer Synchronise onto TX Ethernet clock Sheet.26 Take Timestamp TakeTimestamp Sheet.27 Timestamp for 1-step Timestamp for 1-step 2-D single, open.37 Sheet.29 Sheet.30 Sheet.31 Sheet.32 Timestamp for 1-step and 2-step Timestamp for 1-step and 2-step 2-D single, open.75 Sheet.34 Sheet.35 Sheet.36 Sheet.37 Frame data & Command Field Frame data & Command Field Sheet.38 Modified MAC TX Modified MAC TX 2-D single, open.80 Sheet.40 Sheet.41 Sheet.42 Sheet.43 GMII TX GMII TX Box.44 Existing CRC Existing CRC 2-D single, open.3 Sheet.46 Sheet.47 Sheet.48 Box.99 Insert Checksum & Timestamp Insert Checksum & Timestamp Sheet.50 2-D single, open.34 Sheet.52 Sheet.53 Sheet.54 Box.104 1588 Sample and add known TX latency 1588 Sample and add known TX latency 1 pt arrow.34 Graphic ID: SW & IP X13347 X13347