The previous figure illustrates the 1588 Sample and add known TX latency block. The timestamp is sampled when the Ethernet Start of Frame Delimiter (SFD) is observed at the beginning of the TEMAC transmitter pipeline. This is required to update the UDP Checksum and FCS fields with the timestamp value that is to be inserted in the frame for 1-step operation. For this timestamp to provide reliable system behavior, the following conditions apply.
- The TEMAC contains a fixed latency from the timestamp position onwards through its pipeline.
- The 1000BASE-X core provides a fixed latency for the transmitter path.
- The 7 series FPGA GTX transceiver provides a fixed and deterministic latency through its transmitter path. This is achieved by using the GTX transceiver in TX buffer Bypass mode.
The logic is also then capable of adjusting the ToD timestamp value taken by adding a configurable duration (see bit 22 of Table 2). This value is user adjustable, but its default is initialized with the entire transmitter path latency (through TEMAC, 1000BASE-X, and transceiver).
This results in the returned timestamp default value representing the time at which the SFD can be first observed on the GTX serial transmit output. This latency adjust functionality can be applied to either of the ToD or Correction Field formats.