Using Designer Assistance for the Subsystem - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

After the subsystem is added to the block design canvas, design assistance is enabled and Run Block Automation and Run Connection Automation commands are enabled. See For Kintex UltraScale KCU105 Board.

The Run Block Automation command connects the subsystem AXI4-Stream interface to a DMA or a FIFO as selected in the Vivado IDE. The gtx_clk, ref_clk, and lvds clocks are connected to respective clock sources when the clock source is already present, else it would instantiate a clock wizard. It also connects the mii/gmii/rgmii/sgmii/sfp along with the mdio and phy_rst_n ports based on the interface available for the selected board or part.

Note: You cannot configure the subsystem using the block automation Vivado IDE; therefore, it is recommended first to configure the subsystem and then run block automation.

The axis_clk signal should be connected to the same clock source as the AXI4-Stream interface. When using a FIFO, axis_clk should be connected to the AXI_lite clock of the FIFO; for the DMA this needs to be connected to the same clock source as m_axi_mm2s_aclk and m_axi_s2mm_aclk of DMA.

The Run Connection Automation command connects the AXI4-Lite interface of the subsystem to the peripheral interface of the processor. This also connects the AXI4-Lite clock and the AXI4-Lite reset to the respective sources. When the project is set for a board that has the related interfaces, the Run Connection Automation command also connects the I/Os to external I/O ports by creating them and providing the LOC constraints.