Using the MII Management to Access Internal or External PHY Registers - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

The MII Management interface is used to access PHY registers. These PHYs can either be internal or external to the FPGA. In SGMII and 1000BASE-X modes, the FPGA contains a single PHY. The details of PHY registers can be found in their respective documents. More details are added based on the IEEE standard. For 1000BASE-X PCS/PMA Management registers, see the 1G/2.5G Ethernet PCS/PMA or SGMII LogiCORE IP Product Guide (PG047).

Important: Prior to any MII Management accesses, the MDIO Setup Register must be written with a valid CLOCK_DIVIDE value and the MDIOEN bit must be set.

The value of the PHYAD and REGAD fields in the MII Management Control register determines which PHY registers are accessed. Each PHY, internal or external, should have a unique 5-bit PHY address excluding 00000 which is defined as a broadcast PHY address. The MII Management interface is defined in IEEE Std 802.3, Clause 22 as a two-wire interface with a shared bidirectional serial data bus and a clock with a maximum permitted frequency of 2.5 MHz. As a result, MII Management access can take many AXI4-Lite clock cycles to complete.

To write to a PHY register, the data must be written to the MII Management Data Write register. The PHY address (PHYAD) and PHY register (REGAD) are written to the MII Management Control register. Setting the Initiate bit in the MII Management Control register starts the operation. The format of the PHYAD and REGAD in the MII Management Control register is shown in the following figure.

To read from a PHY register, the PHY address and register number are written to the MII Management Control register. Setting the Initiate bit in the MII Management Control register starts the operation. When the operation completes, the PHY register value is available in the MII Management Read Data register. To access the internal 1G/2.5G Ethernet PCS/PMA or SGMII registers, the PHYAD should match that value set by the parameter C_PHYADDR.

Figure 1. MII Management Write Register Field Mapping AXI Ethernet Page-1 XMLID_2_ Sheet.2 Sheet.3 Sheet.4 Sheet.5 Sheet.6 Sheet.7 XMLID_1_ Sheet.9 Sheet.10 Sheet.11 Sheet.12 Sheet.13 Sheet.14 Sheet.15 Sheet.16 Sheet.17 Sheet.18 Sheet.19 Sheet.20 Sheet.21 REGAD(4:0) REGAD(4:0) Sheet.22 PHYAD(4:0) PHYAD(4:0) Sheet.24 Sheet.25 Sheet.26 Sheet.27 Sheet.28 0 0 Sheet.29 Sheet.30 PCS Sublayer Managed Register Block PCS Sublayer Managed Register Block Sheet.31 Control Register Control Register Sheet.32 PHY (MII Management Interface slave device) PHY (MII Management Interface slave device) Sheet.33 Status Register Status Register Sheet.34 PHY Identifier Register PHY Identifier Register Sheet.35 Phy Identifier Register Phy Identifier Register Sheet.36 0 0 Sheet.37 Sheet.38 1 1 Sheet.39 Sheet.40 2 2 Sheet.41 Sheet.42 Auto negotiation Advertisement Register Auto negotiation Advertisement Register Sheet.43 3 3 Sheet.44 Sheet.45 Sheet.46 Sheet.47 Reserved Reserved Sheet.48 MII Management Control Register MII Management Control Register Sheet.49 MII Management Write Data Register MII Management Write Data Register Sheet.50 16 16 Sheet.51 20 20 Sheet.52 24 24 Sheet.53 28 28 Sheet.54 LSB LSB Sheet.55 15 15 Sheet.56 MSB MSB Sheet.57 REGAD REGAD Sheet.58 Sheet.59 4 4 Sheet.60 31 31 Sheet.61 LSB LSB Sheet.62 16 16 Sheet.63 Write Data Write Data Sheet.64 15 15 Sheet.65 0 0 Sheet.66 MSB MSB Sheet.67 LSB LSB Sheet.68 MSB MSB Sheet.69 Sheet.70 Sheet.71 PHYAD PHYAD Sheet.72 Sheet.73 Sheet.74 ... ... Sheet.23 X14068 X14068

The following table provides an example of a PHY register write through the MII Management Interface.

Table 1. Example of a PHY Register Write Through the MII Management Interface
Register Access Value Activity
MIIM Write Data register WO 0x0000ABCD Write the value that is written to the PHY register (0xABCD in this case).
MII Management Control register WO 0x01024800 Initiate the write to the MII Management Control register by setting the PHYAD (00001), REGAD(00010), OP (01), and Initiate bit (1).
MII Management Control register RO 0x01024880 Poll the MII Management Control register bit 7. When set to 1, the data has been written.
Table 2. Example of a PHY Register Read Through the MII Management Interface
Register Access Value Activity
MII Management Control register WO 0x01028800 Initiate the write to the MII Management Control register by setting the PHYAD (00001), REGAD(00001), OP (10), and Initiate bit (1).
MII Management Control register RO 0x01028880 Poll the MII Management Control register bit 7. When set to 1, the read data is available.
MII Management Read Data register RO Read data provided by PHY register.

After a transfer has been initiated on the MDIO interface, it is also possible to access a non-MDIO register in the memory space normally. The MDIO transfer has completed when the RDY bit in the MII Management Control register is 1. This bit can either be polled, or the interrupt can be monitored.

If the MII Management Control register is rewritten in an attempt to start a new transfer, the data is captured; however, the transfer does not take place until the current transaction completes. If the previous transaction was a read, the read data is valid when the first transaction completes. If the previous transaction was a write, the MII Management Write Data register can be written after the first transaction completes. The MII Management Control register should be checked to ensure all MDIO transactions have been completed before accessing the data or initiating a transfer.