tx_client_fifo - 7.2 English

AXI 1G/2.5G Ethernet Subsystem Product Guide (PG138)

Document ID
PG138
Release Date
2023-11-15
Version
7.2 English

The tx_client_fifo is built around a dual-port inferred RAM, giving a total memory capacity of 4,096 bytes.

When a full frame has been written into the transmit FIFO, the FIFO presents data to the Ethernet MAC transmitter. The Ethernet MAC uses tx_axis_mac_tready to throttle the data until it has control of the medium.

If the FIFO memory fills up, the tx_axis_fifo_tready signal halts the AXI4-Stream interface from writing in data until space becomes available in the FIFO. If the FIFO memory fills up but no full frames are available for transmission, such as when a frame larger than 4,000 bytes is written into the FIFO, the FIFO asserts the tx_overflow signal and continues to accept the rest of the frame. The overflow frame is dropped by the FIFO ensuring that the AXI4-Stream FIFO interface does not lock up.