• aclken : Determines if the core has the aclken pin.
• aresetn : Determines if the core has the aresetn pin.
IMPORTANT: aresetn is active-Low and when asserted, it should be asserted for a minimum of two clock cycles.
• Reset data vector : Specifies if aresetn resets the data vector as well as the control signals. Data vector reset requires additional FPGA logic resources. When no data vector reset has been selected an additional data_valid field is present in the m_axis_data_tuser bus which can be used as further qualification of the output data of the core. See Resets and Input and Output DATA Channels TUSER Options for more details.
• Blank Output : Specifies that the core output will be blanked (forced to zero) following a reset until the data vector is completely filled with new data. This requires minimal additional FPGA logic resources.