This section includes information about using Xilinx ® tools to customize and generate the core in the Vivado® Design Suite.
If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 10] for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value you can run the validate_bd_design command in the Tcl Console.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
1. Select the IP from the IP catalog.
2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 11] and the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 12] .
The FIR Compiler interface in the Vivado IDE contains four pages used to configure the core plus four informational/analysis tabs.
Tool Tips appear when hovering the mouse over each parameter and a brief description appears, as well as feedback about how their values or ranges are affected by other parameter selections. For example, the Coefficient Structure Tool Tip displays the inferred structure when Inferred is selected from the drop-down list.