Demonstration Test Bench in Detail - 7.2 English

FIR Compiler (PG149)

Document ID
PG149
Release Date
2022-10-26
Version
7.2 English

The demonstration test bench performs the following tasks:

Instantiates the core

Generates a clock signal

Drives the input signals of the core to demonstrate core features

Checks that the output signals of the core obey AXI4 protocol rules (data values are not checked to keep the test bench simple)

Provides signals showing the separate fields of AXI4 tdata and TUSER signals

The demonstration test bench drives the input signals of the core to demonstrate the features and modes of operation of the core. An impulse is used as input data in all operations; the corresponding output of the core is therefore the impulse response of the filter, that is, the filter coefficients.

The operations performed by the demonstration test bench are appropriate for the configuration of the generated core, and are a subset of the following operations:

Drive an impulse

Drive an impulse, demonstrating AXI4 handshaking signals by modifying the input data rate using slave data channel TVALID, and modifying the output data rate using master data channel tready (if present)

Drive an impulse, during which deassert clock enable (if present), then assert reset (if present) and drive a new impulse

For multiple paths: drive a set of impulses of different magnitudes on each path

For multiple channels: drive a set of impulses of different magnitudes on each channel

For advanced interleaved data channel sequences: select a different channel pattern; drive an impulse on each channel

For multiple filter coefficient sets: select a different coefficient set (a different set for each channel, if supported); drive an impulse (on each channel, if there are multiple channels)

For reloadable coefficients: load a new coefficient set; drive an impulse (on each channel, if there are multiple channels)