The Implementation Details tab displays Resource Estimation information, core latency, actual calculated coefficients, selected interleaved data channel sequences and the internal structure of AXI4-Stream tdata and TUSER ports.
The number of DSP slices/Multipliers is displayed in addition to a count of the number of block RAM elements required to implement the design. Usage of general slice logic is not currently estimated.
It should be noted that the results presented in the Resource Estimation are estimates only using equations that model the expected core implementation structure. It is not guaranteed that the resource estimates provided in the GUI match the results of a mapped core implementation.
For some configurations, the number of coefficients calculated by the core might be greater than specified. In this circumstance, you can increase the number coefficients used to specify the filter at little or no cost in resource usage.
The AXI4-Port Structure pane describes fields internal to the AXI4-Stream ports and the number of bus transactions the core expects. This pane allows you to see how individual fields map to the indexes of the compound port as a whole.
The Interleaved Channel Pattern pane displays the enumerated list of channel sequences that have been selected. The enumerated value is used to select the desired pattern using the chanpat field of the s_axis_config_tdata port. See CONFIG Channel for details of the CONFIG channel.