Interface Timing - 7.2 English

FIR Compiler (PG149)

Document ID
PG149
Release Date
2022-10-26
Version
7.2 English

This Figure shows the sequence of events from a packet of reload data being written to the RELOAD channel (start of first arrow), which is triggered for use on the arrival and consumption of a packet on the CONFIG channel (end of first arrow and start of second arrow), and on to the data stream.

Note: Particular care should be taken so that the time between the start of the first arrow and the end of the first arrow is sufficient to allow the core to store the new coefficients. When using the Transpose Architecture, this time should be equal to the time required to process a single data input vector (block of interleaved channels).

Figure 3-7: Interface Timing

X-Ref Target - Figure 3-7

fir_reload_reconfig_data_9vOj9iSj_pg149.jpg