The FIR Compiler can build filter implementations that span multiple DSP slice columns. The multi-column implementation is only required when the filter parameters, specifically the number of filter coefficients and the hardware oversampling rate (Sample Frequency to Clock Frequency ratio), result in an implementation that requires to chain together more DSP slices than are available in a single column of the select device. This Figure shows the structures implemented.
The DSP column lengths are displayed on the Details Implementation Options page of the Vivado IDE. The implemented column lengths can be determined automatically, Multi-column Support: Automatic , or user-specified, Multi-column Support: Custom . The length of each implemented DSP column can be specified using the Column Configuration parameter. See Detailed Implementation Tab for more details.