When the required sample frequency is greater than the clock frequency, the core accepts multiple parallel samples every clock cycle for each data channel. The number of parallel samples is determined by calculating the ratio of between the sample frequency and clock frequency.
Super sample rate is supported for single rate and integer rate change configurations. Symmetry is exploited for single rate, polyphase decimator and polyphase interpolator filters.
Note: For rate change filters, symmetry is exploited for a limited range of coefficient/data width, determined by the device selected.