The AXI Quad SPI core can be configured in slave mode by connecting the slave select line of the external master to SPISEL and by setting bit 2 of the SPI control register (SPICR) to 0. Slave mode is allowed only in standard SPI mode. In dual or quad SPI mode, the core only supports master mode.
All incoming signals are synchronized to the AXI clock when the Frequency Ratio parameter is greater than 4. Because of the tight timing requirements when the Frequency Ratio parameter is set to 4, the incoming SCK clock signal and its synchronized signals are used directly in the internal logic. Therefore, the external clock must be synchronized with the AXI clock when the Frequency Ratio parameter is 4. For other Frequency Ratio parameter values, it is preferred, but might not be necessary to have such synchronization.
RECOMMENDED: In slave mode operation, use the FIFO by setting FIFO Depth to 16 or 256 in standard SPI mode.
In slave mode, two interrupts are available in addition to the other interrupts in the IPISR:
•DRR_Not_Empty (bit 8)
•Slave_Mode_Select (bit 7)
Before the other SPI master starts communication, it is mandatory to fill the slave core transmit FIFO with the required data beats. When the master starts communication, with the core configured in slave mode, the core transfers data till the data is available in its transmit FIFO. At the end of last data beat transmitted from the slave FIFO, the core (in slave mode) generates the DTR empty signal to notify that new data beats need to be filled in its transmit FIFO before further communication can start.