Read from a register that does not have all 0s as a default to verify that the interface is functional. Output s_axi_arready asserts when the read address is valid, and output s_axi_rvalid asserts when the read data/response is valid. If the interface is unresponsive, ensure that the following conditions are met:
•The s_axi_aclk and aclk inputs are connected and toggling.
•The interface is not being held in reset, and s_axi_areset is an active-Low reset.
•If the simulation has been run, verify in simulation and/or a Vivado Design Suite debug feature capture that the waveform is correct for accessing the AXI4-Lite interface.
•At a given time, the core will accept either an AXI read or AXI write transaction.