Constraints in Dual Quad Mode - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

In dual quad mode, the STARTUPE3 primitive is enabled. There are 2 SPI interfaces, one is connected to the STARTUPE3 block and the other is connected to the SPI1 (io0_1_,io1_1_,io2_1_,io3_1_ and ss_1_* ports).

The SPI_1 ports are constrained the way shown in STARTUP is Disabled. The rest of the constraints are taken from STARTUP3 is Enabled and based on the Ultrascale and Ultrascale + device family. In Ultrascale devices, the constraints file looks like the following:

# You must provide all the delay numbers

# CCLK delay is 0.5, 6.7 ns min/max for K7-2; refer Data sheet

# Consider the max delay for worst case analysis

set cclk_delay 6.7

# Following are the SPI device parameters

# Max Tco

set tco_max 7

# Min Tco

set tco_min 1

# Setup time requirement

set tsu 2

# Hold time requirement

set th 3

# Following are the board/trace delay numbers

# Assumption is that all Data lines are matched

set tdata_trace_delay_max 0.25

set tdata_trace_delay_min 0.25

set tclk_trace_delay_max 0.2

set tclk_trace_delay_min 0.2

### End of user provided delay numbers

create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_0/ext_spi_clk] -edges {3 5 7} -edge_shift [list $cclk_delay $cclk_delay $cclk_delay] [get_pins -hierarchical *startup*/*usrcclko]

set_multicycle_path -setup -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 2

set_multicycle_path -hold -end -from clk_sck -to [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] 1

set_multicycle_path -setup -start -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 2

set_multicycle_path -hold -from [get_clocks -of_objects [get_pins -hierarchical */ext_spi_clk]] -to clk_sck 1

#create_generated_clock -name clk_sck -source [get_pins -hierarchical *axi_quad_spi_1/ext_spi_clk] [get_ports <SCK_IO>] -edges {3 5 7}

# Data is captured into FPGA on the second rising edge of ext_spi_clk after the SCK falling edge

# Data is driven by the FPGA on every alternate rising_edge of ext_spi_clk

set_input_delay -clock clk_sck -max [expr $tco_max + $tdata_trace_delay_max + $tclk_trace_delay_max] [get_ports IO*_1_IO] -clock_fall;

set_input_delay -clock clk_sck -min [expr $tco_min + $tdata_trace_delay_min + $tclk_trace_delay_min] [get_ports IO*_1_IO] -clock_fall;

# Data is captured into SPI on the following rising edge of SCK

# Data is driven by the IP on alternate rising_edge of the ext_spi_clk

set_output_delay -clock clk_sck -max [expr $tsu + $tdata_trace_delay_max - $tclk_trace_delay_min] [get_ports IO*_1_IO];

set_output_delay -clock clk_sck -min [expr $tdata_trace_delay_min - $th - $tclk_trace_delay_max] [get_ports IO*_1_IO];