Core Behavior in Legacy and Enhanced Non-XIP Mode - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

This mode is set whether or not Enable Performance Mode is selected and when it is, Enable XIP Mode is not selected. The AXI Quad SPI core supports Winbond, Micron, Spansion and Macronix memories. Check the commands if different memories must be tested with the core. If the commands, address, and data behavior are the same for a different memory, that device can be chosen as the base memory to test the core.

The core understands the commands and its expected behavior for the targeted memory through internal logic. The commands which are not supported by the Winbond, Micron, Macronix, and Spansion memory device mentioned in the data sheet are marked with a command error. After the command error is set, the core does not execute the SPI transaction for that command and a command error interrupt is generated. After the command phase, if there is an address phase included, the next DTR contents are transferred on a SPI transaction in the modes defined by the address mode bits. If the data phase is present for the particular command, the data phase is executed based on read or write, with the modes set by the data mode bits.

The dummy bytes, which are required in some of the instructions for the selected memory, should be part of the SPI DTR along with the number of bytes intended to read from memory. For more information on the number of dummy bytes needed for a particular instruction, consult the data sheet for the targeted memory.

For read commands, after the transmission of the address bits, the core immediately reverts to input mode and starts storing data in the DRR. Therefore, be aware of how many dummy bytes are to be ignored in the DRR. For example, for the fast read dual output command in Winbond memory, the DTR should be filled with one command byte plus three address bytes plus two dummy bytes for the dummy cycles plus the number of dummy bytes to be read from memory. The command and address are transferred in standard SPI mode, after which the core reverts to the input mode and starts storing the data. The data is transferred on the IO0_I and IO_1 lines and stored in the SPI DRR, which includes the two dummy cycles plus valid data. Therefore, while reading the SPI DRR, ignore the first 6 bytes of the SPI DRR. The valid data available in the FIFO begins with the seventh byte. This also applies to other dual or quad read commands.

For each fresh transaction, the SPI DTR FIFO must be cleared. The first entry in the SPI DTR is always considered the command entry, which is cross-checked against built-in logic for the respective memory in the selected SPI mode.