Core Behavior in XIP Mode - 3.2 English

PG153 AXI Quad SPI Product Guide

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3.2 English

This mode is set when Enable XIP Mode is selected. This mode is especially useful when using the flash in ROM operations where the executable file is stored and accessed by the processor or any master.

In XIP mode, the core supports 24-bit addressing mode as the common mode across Winbond, Micron, and Spansion devices, while for Micron and Spansion memories the core also supports 32-bit address mode. In 32-bit addressing mode of IP, flash must be configured in 32 bit mode. For the supported command set corresponding flash data sheet can be referred. The 24-bit addressing is applicable to both Winbond and Micron memories with the core in Standard, Dual, and Quad modes.

In this mode, the AXI4-Lite interface is first used to configure the core with the proper CPOL and CPHA modes. The valid modes are 00 and 11. Any other combination causes the core to not accept the AXI4 transaction. The AXI4-Lite interface is only used to set the configuration register and read the status register. The AXI4 interface is used to read the data from memory with the address provided by the AXI4 interface. The read channel of the AXI4 interface should provide the starting address which is converted by the core to the SPI transactions at the SPI interface. The operating mode of the core is set using Mode while the targeted memory is selected based on the Slave Device setting. In this case, a single memory is targeted and multiple memories are not supported by the core. The target memory can be any from Winbond, Micron, or Spansion or any other memory which supports the default three read commands. The maximum burst length for read transaction on AXI4 interface in this mode is 64 as the FIFO depth is 64. The core behavior is not guaranteed otherwise.

The default commands are fast read (0x0Bh), fast read dual I/O (0xBBh) and fast read quad I/O (0xEBh). Based on the setting of Mode, the same command is used throughout the operation. The command cannot be changed as it is generated internally by the core.

The core has internal reference logic, which pads the dummy bytes required for the particular read command.

The XIP mode of core operation is based on the Winbond, Micron, and Spansion memory data sheet specification for read command behavior.

Parameters used for this configuration:

Enable Performance Mode

Enable XIP Mode


Slave Device

Enable STARTUPEn Primitive

Note:   The STARTUPE2 primitive is applicable for 7 series devices. The STARTUPE3 primitive is applicable for UltraScale devices.

The core uses the ext_spi_clk as the reference clock for the SPI logic. This clock is separate from the AXI4 interface clock and it should be double the desired SPI frequency at the SPI interface. The core uses a Frequency Ratio setting of 2, which is fixed for this mode, for generating the SPI clock at the SPI interface with reference to this clock. There is no soft reset register or interrupt register associated with XIP mode. The only way to reset the core is to reset the interconnect.

In this mode, the core supports WRAP as well as INCR type AXI4 transactions only. The FIXED transaction results in an error and the core does not accept the transaction. Instead, the transaction error flag is set in the XIP status register. In this case, the targeted memory is Winbond or Spansion and if the core is configured in quad mode, ensure that the QE bit of the status register of the Winbond memory or the QE bit of the configuration register of the Spansion memory is set prior to the booting the core from SPI flash memory. This should be performed using external programming tools.