In dual or quad mode SPI configuration, based on the type of memory (either Winbond, Micron, or Spansion), the SPI DTR FIFO must be filled prior to the transmission of SPI data beats. Reset both the SPI DTR and DRR FIFOs before filling the new transaction. The SPI DTR FIFO should be filled in command, address, dummy bytes and data order format. The first entry in the SPI DTR FIFO is always compared with the internal command map table and, based on the supported command, the core behavior is determined. If the first entry in the SPI DTR FIFO does not match any commands in the supported command list, the core treats this as an error and SPI transactions do not proceed. An interrupt is also generated for this error.
Always check the supported and unsupported command list for the Winbond, Micron, and Spansion memories (unsupported commands for dual/quad SPI Mode and Winbond, Micron, or Spansion memory). If unsupported commands are executed, the core behavior is not guaranteed. An interrupt is set to indicate a command error, which means that the command does not match any of the supported commands in the core. The core in Dual/Quad mode always sends the command phase of the SPI transaction on a single line i.e., IO0_* ports. 2-2-2 and 4-4-4 (Command, address, and data) SPI modes are not supported in Dual/Quad SPI Configuration of the core.