Dual SPI mode is selected when the Mode option in the Vivado IDE is set to Dual. The relevant parameters in this mode are:
•Mode
•Slave Device
•Enable STARTUPEn Primitive
Note: The STARTUPE2 primitive is applicable for 7 series devices. The STARTUPE3 primitive is applicable for UltraScale™ devices.
•Transaction Width
•No. of Slaves
•FIFO Depth
The properties associated with the FIFO are:
•The depth of the FIFO is based on the FIFO Depth option which has valid values of 16 or 256.
•The width of the FIFO is 8-bits because the page size of the SPI slave memories is always 8-bits.
The behavior of the ports in dual mode is:
•For standard SPI mode instructions, the IO0 and IO1 pins are unidirectional [the same as the master out slave in (MOSI) and master in slave out (MISO) pins].
•For dual mode SPI instructions, the IO0 and IO1 pins are bidirectional — depending on the type of command and memory chosen.
The quad SPI mode is selected when the Mode option is set to Quad. The behavior of the ports in quad SPI mode is:
•For standard mode SPI instructions, the IO0 and IO1 pins are unidirectional and function the same as in standard SPI mode.
•For dual mode SPI instructions, the IO0 and IO1 pins are unidirectional or bidirectional depending on the type of instruction and memory selected by setting the control register bits. The IO2 and IO3-bits are 3-state.
•For quad mode SPI instructions, the IO0, IO1, IO2, and IO3 pins are unidirectional or bidirectional depending on the type of memory used while transmitting the command, address, and data.
When the Mode option is Dual or Quad, the core is forced to operate in dual or quad SPI mode, respectively, while the core continues to support the standard SPI commands and interface. The internal command logic guides the core I/O behavior depending on the command loaded in the DTR FIFO (SPI DTR). The Mode option settings also determine the I/O pin availability.