All SPI transactions in master mode depend upon commands supported by a slave device connected to the AXI QUAD SPI core. Refer to the respective SPI slave data sheet for the supported commands and mode (standard/Dual/Quad). The following steps briefly describe the erase, write and read command sequence for SPI flash.
Note: [1] The WRITE ENABLE command must be issued before every write transaction (erase/write data to the flash/register write of flash) command to the flash.
Note: [2] The following programming sequence is based on the 24-bit addressing mode of flash and assumes there is only one slave connected to the AXI QUAD SPI core.