IP Interrupt Status Register (IPISR)

Up to fourteen unique interrupt conditions are possible depending on whether the system is configured with FIFOs or not, as well as if it is configured in master mode or slave mode. A system without FIFOs has seven interrupts. The 32-bit interrupt status register within the interrupt controller can enable each interrupt independently. The IP Interrupt Status Register (IPISR) collects all of the interrupt events. Bit assignments are shown in This Figure and described in Table: IP Interrupt Status Register Description (Core Base Address + 0x20). The interrupt register is a read/toggle-on-write register. Writing a 1 to a bit position within the register causes the corresponding bit to toggle. All register bits are cleared on reset.

Figure 2-10: IP Interrupt Status Register (Core Base Address + 0x20)
X-Ref Target - Figure 2-10

Table 2-13: IP Interrupt Status Register Description (Core Base Address + 0x20)
Bits	Name	Core Access	Reset Value	Description
31:14	Reserved	N/A	N/A	Reserved
13	Command Error	R/TOW⁽¹⁾	0	Command error. IPISR Bit[13] is the command error. When set to: 1 = This flag is asserted when: •The core is configured in dual/quad SPI mode and •The first entry in the SPI DTR FIFO (after reset) does not match with the supported command list for particular memory. When the SPI command in DTR FIFO does not match with the internal supported command list, the core completes the SPI transactions in standard SPI format. This bit is set to show this behavior of the core. In standard SPI mode this bit is always in default state.
12	Loopback Error	R/TOW⁽¹⁾	0	Loopback error. IPISR Bit[12] is the loopback error. When set to: 1 = This flag is asserted when: •The core is configured in dual or quad SPI transfer mode and •The LOOP bit is set in control register (SPICR(0)). In standard SPI mode, this bit is always in default state.
11	MSB Error	R/TOW⁽¹⁾	0	MSB error. IPISR Bit[11] is the MSB error. When set to: 1 = This flag is asserted when: •The core is configured in either dual or quad SPI mode and •The LSB First bit in the control register (SPICR) is set to 1. In standard SPI mode, this bit is always in default state.
10	Slave Mode Error	R/TOW⁽¹⁾	1	I/O mode instruction error. IPISR Bit[10] is the slave mode error. This flag is asserted when: •The core is configured in either dual or quad SPI mode and •The core is configured in master = 0 in control register (SPICR(2)). In standard SPI mode, this bit is always in default state.
9	CPOL_CPHA Error	R/TOW⁽¹⁾	0	CPOL_CPHA error. IPISR Bit[9] is the CPOL_CPHA error. This flag is asserted when: •The core is configured in either dual or quad SPI mode and •The CPOL - CPHA control register bits are set to 01 or 10. In standard SPI mode, this bit is always in default state.
8	DRR_Not_Empty	R/TOW⁽¹⁾	0	DRR not empty. IPISR Bit[8] is the DRR not empty bit. The assertion of this bit is applicable only in the case where FIFO Depth is 16 or 256 and the core is configured in slave mode and standard SPI mode. This bit is set when the DRR FIFO receives the first data value during the SPI transaction. This bit is set by a one-clock period strobe to the interrupt register when the core receives the first data beat. Note: The assertion of this bit is applicable only when the FIFO Depth parameter is 16 or 256 and the core is configured in slave mode in standard SPI mode. When FIFO Depth is set to 0, this bit always returns 0. This bit has no significance in dual/quad mode.
7	Slave_Select_Mode	R/TOW⁽¹⁾	0	Slave select mode. IPISR Bit[7] is the slave select mode bit. The assertion of this bit is applicable only when the core is configured in slave mode in standard SPI configuration. This bit is set when the other SPI master core selects the core by asserting the slave select line. This bit is set by a one-clock period strobe to the interrupt register. Note: This bit is applicable only in standard SPI slave mode.
6	TX FIFO Half Empty	R/TOW⁽¹⁾	0	Transmit FIFO half empty. In standard SPI configuration, IPISR Bit[6] is the transmit FIFO half-empty interrupt. For example, when FIFO depth = 16, this bit is set by a one-clock period strobe to the interrupt register when the occupancy value is decremented from 1000 to 0111. Note that 0111 means there are 8 elements in the FIFO to be transmitted. In this mode, the FIFO depth is fixed to 16 only. The same logic applies when the FIFO depth is 256 where 10000000 changes to 01111111. In dual or quad SPI configuration, based on the FIFO depth, this bit is set at half-empty condition. Note: This interrupt exists only if the AXI Quad SPI core is configured with FIFOs (In standard, dual or quad SPI mode).
5	DRR Overrun	R/TOW⁽¹⁾	0	Data receive register/FIFO overrun. IPISR Bit[5] is the data receive FIFO overrun interrupt. This bit is set by a one-clock period strobe to the interrupt register when an attempt to write data to a full receive register or FIFO is made by the SPI core logic to complete a SPI transfer. This can occur when the SPI device is in either master or slave mode (in standard SPI mode) or if the IP is configured in SPI master mode (dual or quad SPI mode).
4	DRR Full	R/TOW⁽¹⁾	0	Data receive register/FIFO full. IPISR Bit[4] is the data receive register full interrupt. Without FIFOs, this bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register (An element can be a byte, half-word, or word depending on the value of Transfer Width). With FIFOs, this bit is set at the end of the SPI element transfer, when the receive FIFO has been completely filled by a one-clock period strobe to the interrupt register.
3	DTR Underrun	R/TOW⁽¹⁾	0	Data transmit register/FIFO underrun. IPISR Bit[3] is the data transmit register/FIFO under-run interrupt. This bit is set at the end of a SPI element transfer by a one-clock period strobe to the interrupt register when data is requested from an empty transmit register/FIFO by the SPI core logic to perform a SPI transfer. This can occur only when the SPI device is configured as a slave in standard SPI configuration and is enabled by the SPE bit as set. All zeros are loaded in the shift register and transmitted by the slave in an under-run condition.
2	DTR Empty⁽²⁾	R/TOW⁽¹⁾	0	Data transmit register/FIFO empty. IPISR Bit[2] is the data transmit register/FIFO empty interrupt. It is set when the last byte of data has been transferred out to the external flash memory. See Transfer End Period. In the context of the M68HC11 reference manual, when configured without FIFOs, this interrupt is equivalent in information content to the complement of the SPI transfer complete flag (SPIF) interrupt bit. In master mode if this bit is set to 1, no more SPI transfers are permitted.
1	Slave MODF	R/TOW⁽¹⁾	0	Slave mode-fault error. IPISR Bit[1] is the slave mode-fault error flag. This interrupt is generated if the SS signal goes active while the SPI device is configured as a slave, but is not enabled. This bit is set immediately on SS going active and continually set if SS is active and the device is not enabled.
0	MODF	R/TOW⁽¹⁾	0	Mode-fault error. IPISR Bit[0] is the mode-fault error flag. This interrupt is generated if the SS signal goes active while the SPI device is configured as a master. This bit is set immediately on SS going active.
Notes: 1.TOW = Toggle On Write. Writing a 1 to a bit position within the register causes the corresponding bit position in the register to toggle. 2.Look for the DTR Empty bit in IPISR to make sure that the transaction from the IP to flash memory is complete.

IP Interrupt Status Register (IPISR) - 3.2 English

PG153 AXI Quad SPI Product Guide