•The AXI Quad SPI core supports one memory selection at a time. This means, in multi-slave systems, the core should be configured to select and perform operations only on one slave at a time.
•The core is based on the specific memory parts from Winbond (W25Q80), Micron (N25Q256), Macronix (MX66U1G45G), and Spansion (S70FL01GS). To test the core with other memory parts, ensure that the internal command decoding logic and its bit positions are understood for correct operation of the core.
Also, check the common command set between the Winbond or Micron or Spansion or Macronix memory part data sheet and other memory parts to confirm that the common commands between these documents are executed. In quad mode, the design supports the Micron memory parts with HOLD functionality only. The memory parts with RESET functionality are not supported in the design.
•Dedicated memory should be used as AXI Quad SPI slaves because the core supports a limited set of commands which are common in Winbond, Micron, and Spansion memories in terms of command, address, data requirement and their Macronix behavior. If single dedicated memories are used with the core, a wider range of commands is supported for the respective memory and performance is optimized.
•In XIP mode, there are several clock domain crossing signals present between the AXI4 and AXI4-Lite interfaces and the SPI domain. When reading the XIP SR, note that the core takes five clock cycles to update the status bits.
•XIP configuration mode does not support byte access mode.
•The core does not support queued commands. The core design is based on commands supported by standard SPI devices such as Winbond, Micron, Macronix, and Spansion memory only.