1.Reset RX and TX FIFOs through SPICR.
3.Fill SPIDTR with the dummy data to read required data from the flash.
4.Issue chip select by writing 0x00 to SPISSR(70h).
5.Enable master transaction by deasserting the SPICR master inhibit bit.
6.Deassert chip select by writing 0x01 to SPISSR.
7.Disable master transaction by asserting SPICR master inhibit bit
8.Read SPIDRR, to get the Read data that is received from the SPI bus.