•Enable Master Mode – Enables master SPI mode when checked, slave SPI mode when not checked. The enable master mode parameter is applicable only in standard SPI mode. In dual or quad SPI mode, only master SPI mode is supported.
•Enable FIFO – Includes the transmit or receive FIFO in the design when checked, omits the FIFO when not checked. The enable FIFO parameter is applicable only in standard SPI mode. In dual or quad SPI mode, the FIFO is always included in the design.
•FIFO Depth – Selects the depth of the included FIFO from 0, 16 or 256 beats. In standard SPI mode, this parameter is only available when the FIFO is included. In dual or quad SPI mode, the FIFO depth is limited to either 16 or 256 beats. The FIFO width is fixed at eight bits.
•Enable STARTUPEn Primitive – Includes the STARTUP primitive in the design when checked, omits the primitive when not checked. The STARTUPE2 primitive is featured in 7 series FPGAs and the STARTUPE3 primitive is featured in UltraScale™ devices. It is useful in sharing the SPI clock with an external SPI slave device. This primitive is always disabled in the slave mode of the device.
•Enable Async Clock Mode – Enable this option only when the core is in standalone mode and the AXI interface and external SPI clocks differ in terms of phase/polarity and frequency. This option is disabled in the IP integrator. This parameter is auto propagated depending on the clocks connected to the core. If the AXI clock and ext_spi_clk are synchronous to each other, this parameter is set to 0, It is set to 1 if they are asynchronous to each other.
•Enable Byte Level Interrupt -Enabling this parameter, the “DRR NOT Empty Interrupt” will be triggered on the basis of Byte level instead of transaction level. By default, the value will be set to “0” which means the “Interrupt” will be triggered with respect to the transaction.