The slave operation of the core supports a FIXED burst at the transmit or receive FIFO only. The length of this burst transaction should be based on the FIFO Depth parameter as well as the transmit or receive occupancy register. Take note of this to avoid any overrun or underrun errors of the DTR or DRR FIFO.
Use these steps to successfully complete a SPI transaction:
1.Start from proper state including SPI bus arbitration.
2.Configure the master DGIER and IPIER registers. Also configure the slave DGIER and IPIER registers as required.
3.Write configuration data to the master SPI device SPICR register as required.
4.Write configuration data to the slave SPI device SPICR register as required.
5.Write the active-Low, one-hot encoded slave select address to the master SPISSR register.
6.Write all data to the slave SPI DTR register/FIFO as required.
7.Write all data to the master SPI DTR register/FIFO.
8.Write the enable bit to the master SPICR register which starts the transfer.
9.Wait for interrupt (typically IPISR bit 4) or poll status for completion.
10.Read the IPISR register of both master and slave SPI devices as required.
11.Perform interrupt requests as required.
12.Read the SPISR register of both master and slave SPI devices as required.
13.Perform actions as required or dictated by SPISR register data.