This section describes the SPI protocol where slave select (SS(N)) is asserted automatically (when FIFO is disabled) by the SPI master device (SPICR bit 7 = 0).
This configuration mode is provided to permit transfer of data with automatic toggling of the slave select (SS) signal until all elements are transferred. In this mode, the data in the SPISSR register appears on the SS(N) output when the new transfer starts. After every beat of the SPI transaction (configured through Transaction Width in the Vivado Integrated Design Environment (IDE)), the SS(N) output goes to 1. The data in the SPISSR register again appears on the SS(N) output at the beginning of a new transfer. The slave select signal does not need to be manually controlled. This mode is not supported in dual or quad SPI modes in cores using the AXI4-Lite and AXI4 interfaces.