This section briefly describes the SPI protocol where the slave select, SS(N), is user asserted (that is, SPICR bit 7 = 1). This configuration mode is provided to permit transfers of an arbitrary number of elements without toggling slave select until all the elements are transferred. In this mode, the data in the SPISSR register appears directly on the SS(N) output.
As described earlier, SCK must be stable before the assertion of slave select. Therefore, when manual slave select mode is used, the SPI master must be enabled first (SPICR bit 7 = 1) to put SCK in the idle state prior to asserting slave select.
The master transfer inhibit (SPICR bit 8) can be used to inhibit master transactions until the slave select is asserted manually and all FIFO data registers are initialized as required. This can be used before the first transaction and after any transaction that is allowed to complete.
When the preceding rules are followed, the timing is the same as presented for the automatic slave select assertion mode, with the exception that you control the assertion of the slave select signal and the number of elements transferred. While performing complete memory read or page read operations, the manual slave select mode should be used.