The SPI Transmit FIFO Occupancy Register (TX_FIFO_OCY) is present only if the AXI Quad SPI core is configured with FIFOs (FIFO Depth = 16 or 256). If it is present and if the transmit FIFO is not empty, the register contains a four-bit, right-justified value that is one less than the number of elements in the FIFO (occupancy minus one).
This register is read-only. When written, or read when the FIFO is empty, the register contents are not affected. The only reliable way to determine that the transmit FIFO is empty/full is by reading the Tx_Empty/Tx_Full status bit in the SPI Status Register or the DTR empty bit in the interrupt status register. The transmit FIFO occupancy register is shown in This Figure, while the specifics of the data format are described in Table: SPI Transmit FIFO Occupancy Register Description (Core Base Address + 0x74).