This is a dedicated mode and supports only Micron memories as SPI slave devices. The core supports most of the Micron N25Q256-3V memory quad, dual, and standard SPI commands. Table: SPI Command Core Behavior for Dual Mode and Micron Memory shows the core behavior.
Table 3-10: SPI Command Core Behavior for Dual Mode and Micron Memory
|
Command Type
|
Micron
|
Command Error
|
Core Behavior
|
|
Standard SPI
|
Supported
|
No
|
Standard SPI format
|
|
Standard SPI
|
Not supported
|
Yes
|
No SPI transaction
|
|
Dual mode
|
Supported
|
No
|
Dual mode instruction format as given in the data sheet
|
|
Dual mode
|
Not supported
|
Yes
|
No SPI transaction
|
|
Quad mode
|
Supported
|
No
|
Quad mode instruction format as given in the data sheet
|
|
Quad mode
|
Not supported
|
Yes
|
No SPI transaction
|
|
Notes:
1.The core is designed to support the Micron N25Q256-3V memory device in this mode for all quad, dual and standard commands. See the device data sheet for the command, address, dummy bytes and data bytes requirements for each command and for the command, address and data bits operating details.
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