The SPI device includes these standard features in Standard SPI configuration plus those listed in the Features section of IP Facts:
•Supports multi-master configuration within the FPGA with separated _I, _O, _T representation of 3-state ports.
•Works with N times 8-bit data characters in default configuration. The default mode implements manual control of the SS output using data written to the SPISSR. This appears directly on the SS output when the master is enabled. This mode can only be used with external slave devices. An optional operation can be selected where the SS output is toggled automatically (when FIFO is disabled) with each 8-bit character transfer by the master device using a bit in the SPICR for SPI master devices.
•Multi-master environment supported (implemented with 3-state drivers and requires software arbitration for possible conflict). See AXI4-Lite Interface Functionality in Standard SPI Multi-Master Configuration.
•Multi-slave environment supported (automatic generation of additional slave select output signals for the master).
•Supports maximum SPI clock rates up to one-half the AXI clock rate in master mode and one-fourth the AXI clock rate in slave modes (C_SCK_RATIO = 2 is not supported in slave mode due to the synchronization method used between the AXI and SPI clocks). It is required that the AXI and external clock signals be aligned when configured in slave mode.
•Parameterizable baud rate generator for the SPI clock signal.
•The WCOL flag is not supported as a write collision error as described in the M68HC11 reference manual. Do not write to the transmit register when a SPI data transfer is in progress.
•Back-to-back transactions are supported — multiple, uninterrupted byte/half-word/word transfers can occur provided that the transmit FIFO never gets empty and the receive FIFO never gets full.
•All SPI transfers are full-duplex where an 8-bit data character is transferred from the master to the slave and an independent 8-bit data character is transferred from the slave to the master. This can be viewed as a circular 16-bit shift register in that an 8-bit shift register in the SPI master device is connected to another 8-bit shift register in a SPI slave device.