Follow these steps to test the example design on a KC705 board:
1.Configure the core using the Vivado Integrated Design Environment (IDE) in standalone mode.
2.Implement the example design.
3.Generate the bitstream by selecting the implementation and generate the bitstream option.
The status of the transaction, such as Done, is displayed on F16, while the E18 and G19 pins indicate the AXI Traffic Generator core status. For more reference about these pins, refer to the exdes_xdc.ttcl file. It might be necessary to use the exdes_xdc.ttcl file after you uncomment the LOC constraints. For more information, see Checking Results.
With the external memories targeted as slave SPI, the example design is not supported on the board, but you can test the bitstream with the memory model on a given FPGA.
IMPORTANT: You must set the parameter combinations for checking the core behavior through Vivado IDE options.
The built-in memory model is used as target slave. The memory model and core are configured with the predefined command, address, and data. When the example design simulations are enabled, both the model and the core exchange data.