Before executing the DIOFR (0xBBh) or QIOFR (0xEBh), the core executes the high performance mode command on each power-on reset state. This ensures that the Winbond memory is configured in high-performance mode.
IMPORTANT: When quad mode is set, the Winbond memory must be pre-configured by writing to the status register to set the QE bit to 1.
It is your responsibility to pre-configure the memory. The core does not write anything to the status register. The core assumes that this exercise is completed previously in XIP mode.
When the core is configured in dual or quad mode prior to executing the DIOFR or QIOFR commands, the core performs the high performance command write to the memory on POR before accepting the transaction on the AXI4 interface. The HPM command requires one command and three dummy SPI cycles. This writing of the HPM command in memory is performed only at the power-on condition. The memory is now placed in high performance mode (HPM — 0xA3h) and allows DIOFR or QIOFR to operate in their respective modes.