1.Reset RX and TX FIFOs through SPICR.
3.Fill SPIDTR with the data to be written to flash; the maximum data size depends upon the configured QSPI FIFO size.
4.Issue chip select by writing 0x00 to SPISSR.
5.Enable master transaction by deasserting the SPICR master inhibit bit.
6.Deassert chip select by writing 0x01 to SPISSR.
7.Disable master transaction by asserting the SPICR master inhibit bit.