When the AXI Quad SPI core is configured in XIP mode, only the following registers are available through the AXI4-Lite interface:
These 32-bit registers are configurable and accessible individually through the AXI4-Lite interface. Table: Core Registers in Enhanced Mode XIP Mode provides a summary of the AXI Quad SPI core registers in XIP mode.
IMPORTANT: In XIP mode, the AXI QUAD SPI does not generate any interrupt. The interrupt pin can be left unconnected.