XIP Status Register - 3.2 English

PG153 AXI Quad SPI Product Guide

Document ID
PG153
Release Date
2022-04-26
Version
3.2 English

The bit assignments for the XIP Status Register (XIP-SR) are shown in This Figure and described in Table: XIP Status Register Description (Core Base Address+0x64). This register is used to check the status of commands and other processes performed by the core. In the case where the core receives write commands or write transactions, an error is generated and this is indicated in the status register. This is a read-only register. Any attempt to write to this register completes with a standard acknowledge and the register contents are not updated. The contents of this register are reset as soon as it is read. As there is no timeout counter involved in the core, if the AXI4 transaction is not accepted, check the status registers for any errors. If there are errors, the core does not accept the AXI4 transaction.

Figure 2-13:      XIP Status Register (Core Base Address+0x64)

X-Ref Target - Figure 2-13

pg153_xip_status_register_core_base_address_0_64_x14432.jpg
Table 2-16:      XIP Status Register Description (Core Base Address+0x64)

Bits

Name

Core Access

Reset Value

Description

31:5

Reserved

N/A

0

Reserved

4

AXI Transaction Error

R

0

AXI transaction error

3

CPOL_CPHA Error

R

0

CPOL_CPHA error

2

Master MODF

R

0

Master mode fault. This bit is set to 1 if the spisel line is deasserted.

1

RX Full

R

0

Receiver full

0

RX Empty

R

1

Receiver empty