UltraScale Devices Gen3 Integrated Block for PCI Express LogiCORE IP Product Guide (PG156) - 4.4 English

Document ID: PG156
Release Date: 2022-12-12
Version: 4.4 English

UltraScale Devices Gen3 Integrated Block for PCI Express v4.4 LogiCORE IP Product Guide
IP Facts
Introduction
Features
Overview
Feature Summary
Applications
Unsupported Features
Licensing and Ordering
Product Specification
Resource Utilization
Minimum Device Requirements
A vailable Integrated Blocks for PCI Express
GT Locations
Port Descriptions
AXI4-Stream Core Interfaces
64/128/256-Bit Interfaces
Completer Request Interface
Completer Completion Interface
Requester Request Interface
Requester Completion Interface
Other Core Interfaces
Configuration Management Interface
Configuration Status Interface
Configuration Received Message Interface
Configuration Transmit Message Interface
Configuration Flow Control Interface
Per Function Status Interface
Configuration Control Interface
Configuration Interrupt Controller Interface
Configuration Extend Interface
Clock and Reset Interface
PCI Express Interface
Attribute Descriptions
User Interface
Configuration Space
Designing with the Core
Shared Logic
GT COMMON Option
Shared Logic in the Core
Shared GT_COMMON
Shared GT_COMMON Use Case with GTH
Limitations
GT Wizard Option
Tandem Configuration
Supported Devices
Overview of Tandem Tool Flow
Tandem PROM
Tandem PROM VCU108 Example Tool Flow
Tandem PROM Summary
Tandem PCIe
Tandem PCIe VCU108 Example Tool Flow
Loading Stage 2 Through PCI Express
Tandem PCIe Summary
Tandem with Field Updates
Differences from Tandem Configuration
Design Layout
Design Structure
Tandem Configuration with Field Updates Software Flow
Details on the Sample Design
Details on the Design Scripts
Bitstream Generation
Hardware Operation Details
Debugging Tandem with Field Updates Designs
Important Considerations
Known Limitations
Using Tandem With a User Hardware Design
Method 1 – Using the Existing PCI Express Example Design
Method 2 – Migrating the PCIe Design into a New Vivado Project
Tandem Configuration RTL Design
MUXing Critical Inputs
TLP Requests
Tandem Configuration Logic
User Application Handshake
Tandem Configuration Details
I/ O Beh a vior
Configu r a t io n Pi n Beh a vior
Configuration P e r si s t (Tandem PROM Only)
Avoiding the Configuration Bank
P R O M Selection
P r og r ammin g th e D e vice
Bitstream Encryption
Tandem PROM/PCIe Resource Restrictions
Moving the PCIe Reset Pins
Non-Project Flow
Simulating the Tandem IP Core
Calculating Bitstream Load Time for Tandem
Example 1
Example 2
Using Bitstream Compression
Other Bitstream Load Time Considerations
Case 1: Without ATX Supply
Case 2: With ATX Supply
Sample Bitstream Sizes
Clocking
Resets
AXI4-Stream Interface Description
Feature Overview
Data Alignment Options
Straddle Option on RC Interface
Receive Transaction Ordering
Transmit Transaction Ordering
Completer Interface
Completer Request Interface Operation
Completer Request Descriptor Formats
Completer Memory Write Operation
Completer Memory Read Operation
I/O Write Operation
I/O Read Operation
Atomic Operations on the Completer Request Interface
Message Requests on the Completer Request Interface
Aborting a Transfer
Selective Flow Control for Non-Posted Requests
Completer Completion Interface Operation
Completer Completion Descriptor Format
Completions with Successful Completion Status
Aborting a Completion Transfer
Completions with Error Status (UR and CA)
Requester Interface
Requester Request Interface Operation
Requester Request Descriptor Formats
Requester Memory Write Operation
Non-Posted Transactions with No Payload
Non-Posted Transactions with a Payload
Message Requests on the Requester Interface
Aborting a Transfer
Tag Management for Non-Posted Transactions
Avoiding Head-of-Line Blocking for Posted Requests
Maintaining Transaction Order
Requester Completion Interface Operation
Requester Completion Descriptor Format
Transfer of Completions with no Data
Transfer of Completions with Data
Straddle Option for 256-Bit Interface
Aborting a Completion Transfer
Handling of Completion Errors
Power Management
Active State Power Management
Programmed Power Management
PPM L0 State
PPM L1 State
PPM L3 State
Generating Interrupt Requests
Legacy Interrupt Mode
MSI Mode
MSI-X Mode
Receive Message Interface
Configuration Management Interface
Link Training: 2-Lane, 4-Lane, and 8-Lane Components
Link Partner Supports Fewer Lanes
Lane Becomes Faulty
Lane Reversal
Design Flow Steps
Customizing and Generating the Core
Basic Mode Parameters
Basic Tab
Component Name
Mode
PCIe Device / Port Type
PCIe Block Location
Number of Lanes
Maximum Link Speed
AXI-ST Interface Width
AXI-ST Interface Frequency
AXI-ST Alignment Mode
Enable AXI-ST Frame Straddle
Enable Client Tag
Reference Clock Frequency
Xilinx Development Board
Enable External PIPE Interface
Additional Transceiver Control and Status Ports
Capabilities Tab
Enable Physical Function 0
PF0 Legacy Interrupt PIN
MPS
Extended Tag
Slot Clock Configuration
Identity Settings (PF0 IDs and PF1 IDs) Tab
PF0 ID Initial Values
Class Code
Class Code Look-up Assistant
Base Address Registers (PF0 and PF1) Tab
Base Address Register Overview
Expansion ROM Base Address Register
Managing Base Address Register Settings
Disabling Unused Resources
Legacy/MSI Cap abilities Tab
Legacy Interrupt Settings
MSI Capabilities
Advanced Mode Parameters
Basic Tab
Enable Parity
Use the dedicated PERST routing resources
System reset polarity
PCIe DRP Ports
GT Channel DRP
Enable RX Message INTFC
Enable GT Quad Selection
GT Quad
CORE CLOCK Frequency
Capabilities Tab
SRIOV Capabilities
Function Level Reset
Device Capabilities Registers 2
PF0 ID and PF1 ID Tab
PF0 BAR and PF1 BAR Tab
SRIOV Config (PF0 and PF1) Tab
SRIOV Cap ability Version
SRIOV Function Select
SRIOV Functional Dependency Link
SRIOV First VF Offset
SRIOV VF Device ID
SRIOV Supported Page Size
PF0 SRIOV BARs and PF1 SRIVO BARs Tab
SRIOV Base Address Register Overview
Managing SRIOV Base Address Register Settings
Disabling Unused Resources
Legacy/MSI Capabilities Tab
MSI‐X Capabilities Tab
Enable MSIx Capability Structure
MSIx Table Settings:
MSIx Pending Bit Array (PBA) Settings
Power Management
Extended Capabilities 1 and Extended Capabilities 2
Additional Optional Capabilities
GT Settings Tab
PLL Selection
Enable Auto RxEq
Form Factor Driven Insertion Loss Adjustment
Link Partner TX Preset
Receiver Detect
GT DRP Clock Source
Disable GT Channel LOC Constraints
Shared Logic
Core Interface Parameters
Transmit FC Interface
Config FC Interface
Config External Interface
Config Status Interface
Per Function Status Interface
Config Management Interface
Receive Message Interface
Config Transmit Message Interface
Physical Layer Interface
Config Interface
Config Control Interface
Add. Debug Options
Enable In System IBERT
Enable Descrambler for Gen3 Mode
Enable JTAG Debugger
Output Generation
Constraining the Core
Required Constraints
Device, Package, and Speed Grade Selections
Clock Frequencies
Clock Management
Clock Placement
Banking
Transceiver Placement
I/O Standard and Placement
Relocating the Integrated Block Core
Simulation
PIPE Mode Simulation
Post-Synthesis/Post-Implementation Netlist Simulation
Post-Synthesis Netlist Functional Simulation
Post-Implementation Netlist Functional Simulation
Synthesis and Implementation
Example Design
Overview of the Example Design
Integrated Block Endpoint Configuration Overview
Simulation Design Overview
Implementation Design Overview
Example Design Elements
Programmed Input/Output: Endpoint Example Design
System Overview
PIO Hardware
Base Address Register Support
Changing IP Catalog Tool Default BAR Settings
TLP Data Flow
Memory and I/O Write TLP Processing
Memory and I/O Read TLP Processing
PIO File Structure
PIO Operation
PIO Read Transaction
PIO Write Transaction
Device Utilization
Configurator Example Design
System Overview
Configurator Example Design Hardware
Configurator Block
Configurator ROM
PIO Master
Configurator File Structure
Summary
Generating the Core
Simulating the Example Design
Endpoint Configuration
Synthesizing and Implementing the Example Design
Test Bench
Root Port Model Test Bench for Endpoint
Architecture
Scaled Simulation Timeouts
Test Selection
Verilog Test Selection
Waveform Dumping
For information on simulator waveform dumping, see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 18] .
Verilog Flow
Output Logging
Parallel Test Programs
Test Description
Test Program: pio_writeReadBack_test0
Expanding the Root Port Model
Root Port Model TPI Task List
Endpoint Model Test Bench for Root Port
Architecture
Simulating the Design
Scaled Simulation Timeouts
Waveform Dumping
For information on simulator waveform dumping, see the Vivado Design Suite User Guide: Logic Simulation (UG900) [Ref 18] .
Output Logging
Upgrading
Upgrading in the Vivado Design Suite
Parameter Changes
Port Changes
Migrating From a 7 Series Gen2 Core to an UltraScale Device Gen3 Core
PCIe 3.1 AXI4 ST Enhanced Interface
Completer Request (CQ) Interface
m_axis_rx_tstrb (64-Bit Interface Only)
m_axis_rx_tuser
AXI4-Stream Requester Completion (RC) Interface
m_axis_rx_tstrb (64-Bit Interface Only)
m_axis_rx_tuser
AXI4-Stream (Enhanced) Completer Completion Interface
s_axis_tx_tstrb
s_axis_tx_tuser
AXI4-Stream Requester Request Interface
s_axis_tx_tstrb
s_axis_tx_tuser
tx_buf_av
Other Interfaces
Package Migration of UltraScale Devices PCI Express Designs
Placement Rules
GTH Location
Stacked Silicon Interconnect (SSI) Devices
Creating a Migration Plan for PCI Express
Migrating Tandem Configuration
G T Locations
Virtex UltraScale Devices Available GT Quads
K intex UltraScale Devices Available GT Quads
Managing Receive-Buffer Space for Inbound Completions
General Considerations and Concepts
Completion Space
Maximum Request Size
Read Completion Boundary
Important Note For High Performance Applications
Methods of Managing Completion Space
LIMIT_FC Method
PACKET_FC Method
RCB_FC Method
DATA_FC Method
Debugging
Finding Help on Xilinx.com
Documentation
Answer Records
Technical Support
Hardware Debug
Transceiver Control and Status Ports
Using The Xilinx Virtual Cable to Debug
Introduction
Overview
Host PC XVC-Server Application
Host PC XVC-over-PCIe Driver
XVC-over-PCIe Enabled FPGA Design
XVC-over-PCIe Through PCIe Extended Configuration Space (PCIe-XVC-VSEC)
XVC-over-PCIe Through AXI (AXI-XVC)
XVC-over-PCIe Register Map
PCIe Ext Capability Header
PCIe VSEC Header (PCIe-XVC-VSEC only)
XVC Version Register
XVC Shift Length Register
XVC TMS Register
XVC TDO/TDI Data Register(s)
XVC Control Register
XVC Status Register
XVC Driver and Software
Special Considerations for Tandem or Dynamic Function eXchange Designs
Using the PCIe-XVC-VSEC Example Design
Generating a PCIe-XVC-VSEC Example Design
System Bring-Up
Compiling and Loading the Driver
Compiling and Launching the XVC-Server Application
Connecting the Vivado Design Suite to the XVC-Server Application
Run Time Considerations
Additional Resources and Legal Notices
Xilinx Resources
Documentation Navigator and Design Hubs
References
Revision History
Please Read: Important Legal Notices

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