The GMII to RGMII IP core is designed for use with the Gigabit Ethernet embedded blocks in the Zynq-7000 SoC and Zynq® UltraScale+™ MPSoC devices. The Gigabit Ethernet MAC embedded blocks present in the Zynq-7000 SoC or Zynq® UltraScale+™ MPSoC device would provide an RGMII interface through the Multiplexed I/O pins (MIO) and a GMII interface through the EMIO interface to route through the Programmable Logic (PL). The GMII to RGMII IP can be used to provide an RGMII interface using the PL. For more information on the device-specific Gigabit Ethernet Controller, see the Xilinx Zynq-7000 SoC Technical Reference Manual [Ref 1] and Zynq UltraScale+ MPSoC Technical Reference Manual [Ref 11].