This section includes information about using Xilinx® tools to customize and generate the core in the Vivado Design Suite.
If you are customizing and generating the core in the IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) [Ref 3] for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To determine whether the values change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl Console.
The GMII to RGMII core is generated using the IP catalog.
All parameters available for the core in the IP catalog are also available in the IP integrator. The Vivado Integrated Design Environment (IDE) is identical, so settings that apply to the core in IP catalog also apply for the IP integrator.
You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:
1.Select the IP from the IP catalog.
2.Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.
For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) [Ref 5] and the Vivado Design Suite User Guide: Getting Started (UG910) [Ref 6].
Note: Figures in this chapter are illustrations of the Vivado IDE. This layout might vary from the current version.
This Figure displays the GMII to RGMII customization screen used to set core parameters and options.
•Component Name – The component name is used as the base name of the output files generated for the core. Names must begin with a letter and can be composed of the following characters: a through z, 0 through 9, and the underscore (_).
•External Clock – Select this option to source the GMII clock externally. When selected, ensure that the GMII clock frequency is appropriate for the line rate: 2.5 MHz for 10 Mb/s, 25 MHz for 100 Mb/s, and 125 MHz for 1,000 Mb/s.
By default, the GMII clock is generated internally. The GMII to RGMII IP has a built-in clock generator for providing 2.5 MHz, 25 MHz, and 125 MHz frequency clocks for 10 Mb/s, 100 Mb/s, and 1,000 Mb/s speeds of operation, respectively.
•Instantiate IDELAYCTRL in the Design – Select this option to instantiate an IDELAYCTRL primitive in the core. The IDELAYCTRL primitive should be instantiated when Input/Output Delay primitives are used in the design. This core uses them, and thus this option is selected by default.
If your design has an IDELAYCTRL primitive instantiated for the I/O bank to which the RGMII I/Os are also mapped, then you should not select this option.
The IDELAYCTRL primitive is instantiated as part of the Shared Logic and is part of the core in the Include Shared Logic in the Core configuration. If only one instance of the core exists in the Include Shared Logic in the Example Design configuration, the IDELAYCTRL primitive needs to be instantiated in the design.
Note: IDELAYCTRL is not needed for the Versal device.
•PHY Address – The PHY Address is the 5-bit address used to identify the core in a MDIO transaction. Valid ranges are 0 to 31. The PHY address here must be different from the address assigned to the onboard PHY.
•Provide 2 ns Skew on RGMII TXC – Select this option to choose the location where 2 ns skew on RGMII TXC is added with respect to RGMII TXD. If the skew is added in the FPGA, it can be by ODELAYs (present in devices HPIOs only) or through MMCM.
IMPORTANT: This option of using ODELAY can be used only when the RGMII TXC pin is mapped to a high-performance I/O Bank on the device.