The 200/375 MHz free-running clock is used as a reference clock to the IDELAYCTRL primitive (when enabled in the core), input to the GMII TX clock generator module (when GMII clock is sourced internally), and clock the management modules. The Shared Logic option determines how this clock is handled in the core.
This Figure depicts the clocking scheme when the Shared Logic in Core option is selected. The 200/375 MHz free-running clock, shown as clk_in, is routed through the global clock buffer (BUFG) and then used in the core. It is also an output of this core that can be used by other instances of the GMII to RGMII cores that are configured for the shared logic to be present in the example design. This allows the sharing of the clock resources.