The Xilinx® LogiCORE™ IP Gigabit Media Independent Interface (GMII) to Reduced Gigabit Media Independent Interface (RGMII) core provides the RGMII between RGMII Ethernet physical media devices (PHY) and the Gigabit Ethernet controller (GEM) in the Zynq®-7000 SoCs, Gigabit Ethernet soft IP in Versal™ device, and Zynq® UltraScale+™ MPSoCs. This core can be used in all three modes of operation (10/100/1000 Mb/s). The Management Data Input/Output (MDIO) interface is used to determine the speed of operation. This core can switch dynamically between the three different speed modes.