Navigating Content by Design Process - 4.1 English

GMII to RGMII Product Guide (PG160)

Document ID
PG160
Release Date
2022-06-15
Version
4.1 English

Xilinx® documentation is organized around a set of standard design processes to help you find relevant content for your current development task. This document covers the following design process:

Hardware, IP, and Platform Development: Creating the PL IP blocks for the hardware platform, creating PL kernels, subsystem functional simulation, and evaluating the Vivado® timing, resource use, and power closure. Also involves developing the hardware platform for system integration. Topics in this document that apply to this design process include:

°Port Descriptions

°Register Space

°Clocking and Resets

°Customizing and Generating the Core

°Constraining the Core

°Example Design