If you wish to instantiate the AXI4-Lite interface to access the control and status registers of the CMAC core, you need to tick mark the Include AXI4-Lite Control and Statistics Interface check box in the General Tab . It enables the axi4_lite_if_wrapper module (that contains axi4_lite_reg_map along with the axi4_lite_slave_2_ipif module) in the cmac_wrapper . The user interface logic for accessing the registers (control, status and statistics) is present in the pkt_gen_mon module.
Note: In the CAUI-4 mode, if you select Include IEEE 802.3bj RS-FEC along with the Include AXI4-Lite Control and Statistics Interface option, the AXI Crossbar module is instantiated to access the AXI4-Lite interface control and statistics registers for both CMAC and IEEE 802.3bj RS-FEC IP. Refer to IEEE 802.3bj RS-FEC Integration for more details.
This mode enables the following features:
• You can configure all the CTL ports of the core through the AXI4-Lite interface. This operation is performed by writing to a set of address locations with the required data to the register map interface. The address location with the configuration register list is mentioned in Table: Configuration Register Map .
• You can access all the status and statistics registers from the core through the AXI4-Lite interface. This is performed by reading the address locations for the status and statistics registers through register map. Table: Status and Statistics Register Map shows the address with the corresponding register descriptions.
The following diagram shows the implementation when Include AXI4-Lite Control and Statistics Interface is enabled in the General tab.
X-Ref Target - Figure 5-12 |
The following sections provide the AXI4-Lite interface state machine control and ports.